1. Field of the Invention
The present invention relates to a layout of memory cells of a ferroelectric memory.
2. Description of the Related Art
One of the cell array structures of a ferroelectric memory is a TC parallel unit serial connection type. This type has a structure in which a plurality of cell units constituted of parallely connected cell transistors (T) and capacitors (C). This structure is now a focus of attention as a structure capable of realizing a large memory capacity.
Recently, to meet a demand for a lower voltage of the ferroelectric memory, there has been proposed a CMOS type cell transistor in which a cell transistor comprises an N channel MOS transistor and a P channel MOS transistor (e.g., see Jpn. Pat. Appln. KOKAI Publication No. 11-177036).
In this case, however, an increase inevitably occurs in cell size because the cell transistor is the CMOS type.